Typically for a Sonet/SDH framer, a significant portion of the logic associated with an incoming optical line is clocked using a clock signal derived from that line. The blocks clocked at this ‘line rate’ would typically be Section Overhead extraction, High Order Pointer Interpretation and the write function of the High Order Elastic Store.
FIG. 1 illustrates a typical frame architecture in accordance with the prior art. As shown in FIG. 1, the line CDR block is recovering the clock and data from the in-coming data traffic. The line framer is finding the framing bytes (e.g. A1 and A2 bytes) to determine the location of all of the other overhead bytes. As illustrated, the line framer in the conventional architecture is single channel.
The network information of the SDH frame has to be separated from the actual frame data (customer data traffic) at this stage. The system converts the data onto a different clock rate without losing any of the information. Typically, the transport overhead is extracted within the line clock domain. The high order pointer processing moves the customer's data from the line clock domain into the system clock domain. In order to avoid losing any of the information, a set of pointers is examined that indicate where the data is located inside the overall container. This ensures that all of the customer data is put into the elastic store. Within the system clock domain, the pointer generator is responsible for taking that data out of the high order elastic store (typically a set of 12-48 FIFOs) and handling any frequency changes. That is, the in-coming data rate could be 10 PPM faster or slower than the system clock domain rate. An in-coming rate faster than the system clock, may result in lost data. So, what the combination of the higher order pointer processor, elastic store, and pointer generator will do is produce output data, that accommodates any frequency offsets. Therefore, a conventional system supporting multiple optical interfaces requires a large number of clock domains each having a significant number of logic elements. Furthermore, since each block of logic is on a separate clock domain, logic elements cannot be shared between channels, and must be implemented separately for each channel.
A further disadvantage of conventional architecture is that they typically employ separate high order and low order pointer processors that require a large number of logic elements to perform each function. As shown in FIG. 1, the low order pointer processor uses the high order pointer processor to identify the location of the low order pointers. Since any individual byte cannot be part of both pointer types, the operation of large portions of these blocks are similar and mutually exclusive. That is, when processing high order pointers, the elements responsible for low order processing are idle and vice-versa, so the conventional architecture is inefficient in terms of logic.